View HD74HC166_4308236.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

HD74HC166
Parallel-load 8-bit Shift Register
REJ03D0582-0300 Rev.3.00 Jan 31, 2006
Description
This device is an 8-bit shift register with an output from the last stage. Data may be loaded into the register either in parallel or in serial form. When the Shift/Load input is low, the data is loaded asynchronously in parallel. When the Shift/Load input is high, the data is loaded serially on the rising edge of either clock inhibit or Clock. Clear is asynchronous and active-low. The 2-input NOR clock may be used either by combining two independent clock sources or by designating one of the clock inputs to act as a clock inhibit.
Features
* * * * * * High Speed Operation: tpd (Clock to QH) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name HD74HC166P HD74HC166FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP -- EL (2,000 pcs/reel) Taping Abbreviation (Quantity)
Note: Please consult the sales office for the above package availability.
Function Table
Inputs Clear Shift/Load Clock Inhibit Parallel Clock Serial A *** H Internal outputs QA QB L QB0 b QAn QAn QB0 Output QH L QH0 h QGn QGn QH0
L X X X X X L H X L L X X QA0 X a *** h a H L L H X H H H L L X L H H L X X QA0 H X H QAo to QHo = Outputs remain unchanged. QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input. H: High level L: Low level X: Irrelevant
Rev.3.00, Jan 31, 2006 page 1 of 6
HD74HC166
Pin Arrangement
Serial 1 Input A2 B3 Parallel Inputs C4 D5 Clock Inhibit 6 Clock 7 GND 8 (Top view)
16 VCC 15 Shift/Load Parallel 14 Input H 13 Output QH 12 G 11 F 10 E 9 Clear Parallel Inputs
Timing Diagram
Clock Clock Inhibit Clear Serial Input Shift/Load A B C D Parallel Inputs E F G H Output QH Serial Shift Clear Inhibit Load H L H L H L H H H H L H L H L H L
Serial Shift
Rev.3.00, Jan 31, 2006 page 2 of 6
HD74HC166
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Note: Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Unit V V C ns Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 VIL 2.0 4.5 Output voltage VOH 6.0 2.0 4.5 6.0 4.5 6.0 VOL 2.0 4.5 6.0 4.5 Input current Quiescent supply current Iin ICC 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A V IOH = -4 mA IOH = -5.2 mA Vin = VIH or VIL IOL = 20 A V Vin = VIH or VIL IOH = -20 A V V Test Conditions
Rev.3.00, Jan 31, 2006 page 3 of 6
HD74HC166
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Ta = 25C Ta = -40 to +85C Unit Min Typ Max Min Max -- -- -- -- -- -- -- -- -- 150 30 26 100 20 17 5 5 5 80 16 14 -- -- -- -- -- -- -- -- 14 -- -- 12 -- -- 2 -- -- 1 -- -- 0 -- -- 6 -- -- 5 -- 5 5 25 29 175 35 30 150 30 26 -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 -- -- -- -- -- -- -- -- -- 190 38 33 125 25 21 5 5 5 100 20 17 -- -- -- -- 4 20 24 220 44 37 190 38 33 -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 MHz Test Conditions
tPHL, tPLH
ns
Clock to QH
tPHL
ns
Clear to QH
Setup time
tsu
ns
Shift/Load to Clock
ns
Data to Clock
Hold time
th
ns
Clock to Data
Pulse width
tw
ns
Clock, Clear
Output rise/fall time Input capacitance
tTLH, tTHL
ns
Cin
pF
Rev.3.00, Jan 31, 2006 page 4 of 6
HD74HC166
Test Circuit
Measurement point
CL*
Note: CL includes the probe and fig capacitance.
Waveforms
tW VCC Clear
50% 50%
tn Clock
50% 50%
tn+1
tn
tn+1
0V VCC
50%
50%
tW tsu Data tPHL Output QH
50% 50%
0V th
50% 50%
tsu
th VCC
50%
0V tPLH
50%
tPHL VOH
50%
VOL Notes 1. Input wavwform : PRR 1 MHz Zo = 50 tr 6 ns tf 6 ns 2. Propagation delay time (tPLH and tPHL)are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test. 3. tn : bit time before clocking transition. tn+1 : bit time after one clocking transition. tn+8 : bit time after eight clocking transition.
Rev.3.00, Jan 31, 2006 page 5 of 6
HD74HC166
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.3.00, Jan 31, 2006 page 6 of 6
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 205, AZIA Center, No.133 Yincheng Rd (n), Pudong District, Shanghai 200120, China Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Colophon .5.0

▲Up To Search▲

Price & Availability of HD74HC166

	To Download HD74HC166 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .